List of IP Blocks
# | IP Name (Click for Datasheet) | IP Description | Test Chip | Packaged Parts | Testing Status | Process | Application | Differentiation |
RF | ||||||||
1 | An up to 60GHz fully differential frequency divider by 2. Includes: input active balun and I/Q outputs. | PMCC810 | QFN 20pin | Test is done on bare die to measure the maximum dividing frequency. | TowerJazz 0.18um SiGe SBC18HX | PLLs, Broadband test and measurement equipment | Ultra high frequency prescaler on 0.18um SiGe. DC to 60GHz, SE or DIFF inputs, I/Q DIFF outputs. | |
2 | 50GHz Programmable Prescaler -Divider by 1/2/4/8/16 | PMCC800 | QFN 20pin | Test is done: maximum frequency and power is verified. | TowerJazz 0.18um SiGe SBC18HX | PLLs, Broadband test and measurement equipment | DC to 50GHz, programmable dividing coefficients SE or DIFF input, DIFF output. | |
3 | 25.5GHz Colpitts VCO | PMCC900 | None | Tested | TowerJazz 0.18um SiGe SBC18HX | PLLs, Broadband test and measurement equipment | Low noise differential architecture. Low cost process 0.18um SiGe. | |
4 | 24GHz Colpitts VCO | PMCC904 | None | TowerJazz 0.18um SiGe SBC18HX | PLLs, Broadband test and measurement equipment | Low noise differential architecture. Low cost process 0.18um SiGe. | ||
5 | PMCC_REFS | Band-gap and PTAT current reference | Tested on an ASIC | None | Tested | IBM 65nm 10LPe | RF, Analog, Mixed-Signal ICs | BG/PTAT. Multiple outputs referenced to internal and external resistors. Current programmable within +/-30% |
6 | The IP block is a low noise multi-band differential LC voltage controlled oscillator (VCO). | Tested on an ASIC | Tested | IBM 65nm 10LPe | Phase-locked loops. CMU for fiber optic applications. Reference clock generators | Extra low power. Wide frequency range. When used in CMU supports different clocking modes: FEC+G.709, FEC only, G.709, FEC to G709 frame. | ||
7 | PMCC_XCM_64X64_A | An array of 128 ADC 2-bit 1GSps. Each ADC includes a VGA front end. | Cross-correlator ASIC for NASA | Tested as part of a cross-correlator ASIC. | 45nm IBM SOI CMOS technology. | Cross-correlator ASICs for synthetic radar receivers, radiometers and spectrometers. | Ultra low power (~0.5W for entire array). 1GSps. BW=10MHz to 500MHz | |
8 | PMCC_XCM_64X64 | Complete Cross-Correlator With 64×2 Channels | Cross-correlator ASIC for NASA | Thermally enhanced BGA | Tested as part of a cross-correlator ASIC. | 45nm IBM SOI CMOS technology. | Cross-correlator ASICs for synthetic radar receivers, radiometers and spectrometers. | Ultra low power (~1.5W for entire array). 1GSps. BW=10MHz to 500MHz |
Fiber Optics | ||||||||
10 | EA/MZ modulator driver for up-to 11.3Gb/s. Programmable output voltage swing and offset (bias), monitoring, crossing point control. | TowerJazz 0.18um SiGe SBC18HX | EA and MZ modulators and DFB lasers for fiber optic communications; broadband high output swing Limiting Amplifiers from DC to 12Gb/s. | 3V adjustable swing and DC offset. Cross point monitoring and adjusting. Low cost SiGe implementation. | ||||
11 | Robust 8.5-11.3Gb/s data/clock recovery independent on data coding. Deserializing 1:32. | Tested on a fiber optic TRx ASIC | Tested on a fiber optic transceiver ASIC | IBM 65nm 10LPe | 10GbE, OC-192, FC receiver/CDR and deserializer.10G back planes. XFI receiver with deserialization (both line and host side) | Based on CML logic. Ultra low power, 15mV input sensitivity. 65nm CMOS technology. Includes CDR, Equalizer, LOS, LOL, frac N divider. | ||
12 | The IP block is designed for robust 32:1 serialization of 8.5-11.3Gb/s data independent on data coding. | Tested on a fiber optic TRx ASIC | Tested on a fiber optic transceiver ASIC | IBM 65nm 10LPe | SONET/SDH OC-192 transmitter with CMU. PHY 10GbE transmitter. 10G back planes. XFI transmitter with serialization (both line and host side) | Based on CML logic. Line rate output data retiming. Low power, 1V DIFF output swing. 65nm CMOS technology. Includes CMU, with frac N PLL. | ||
13 | The IP block is a Serializer and deserializer designed for robust 32:1 /1:32 serialization of 8.5-11.3Gb/s data independent on data coding. | Tested on a fiber optic TRx ASIC | Tested on a fiber optic transceiver ASIC | IBM 65nm 10LPe | SONET/SDH OC-192 Tx and Rx with CDR/CMU. PHY 10GbE transceiver. 10G back planes. XFI TRx with serialization and deserialization (both line and host side) | Extra low power. CML logic – high noise immunity. Line rate output data retiming. 1V DIFF output swing. 65nm CMOS. Includes CMU, with frac N PLL. | ||
14 | The IP block is designed as a complete CMU X32 producing 8.5-11.3GHz output clock | ASIC | Tested on a fiber optic transceiver ASIC | IBM 65nm 10LPe | 10GbE, FC, OC-192 compliant transceivers supporting multiple clocking mode | Extra low power. CMU supports different clocking modes: FEC+G.709, FEC only, G.709, FEC to G709 frame. | ||
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