12-bit 32 Channel 500MSps Low Latency ADC. 2019
12-bit 32 channel 500MS/s low-latency ADC for particle accelerators real-time control. Fall Meeting of the APS Division of Nuclear Physics. 2017
SBIR/STTR Firm and Award Details
NASA Tech Briefs Magazine, April 2016
Patent for digitizing + correlation ASIC granted, April 2016
NASA has awarded Pacific Microchip Corp. a Phase II grant for development of a digitizer array ASIC., July 13, 2011
An 11.1 Gbps Analog PRML Receiver for Electronic Dispersion Compensation of Fiber Optic Communications” IEEE Journal of Solid-State Circuits, Vol 45, No.7. pp. 1330-1244, July 2010
A 1.6–3.2-GHz Sixth-Order +13.1-dBm OIP3 Linear Phase Gm-C Filter for Fiber-Optic EDC Receivers” IEEE Transactions on Microwave Theory and Techniques, Vol 58, No5. pp. 1314-1322, May 2010
Thermal Gradient and IR Drop Aware Design Flow for Analog Intensive ASICS. Pacific MicroCHIP Corp. AIMS-CAT November, 2009
An 11.1Gbps Analog PRML Receiver for EDC of up to 400km-Reach WDM Fiber-Optic Links. Proceedings of the 35th European Solid–State Circuits Conference (ESSCIRC), pp. 376-379, September 2009
A 12.5Gbps Analog Timing Recovery System for PRML. IEEE RFIC Symp. Dig. Tech. Papers, pp. 535-538, June 2009
Verilog-A Modeling of DFFs in CDRs. White Paper. Pacific MicroCHIP Corp. June 2009
A Monolithic One-sample/bit Partial-Response Maximum Likelihood SiGe Receiver for Electronic Dispersion Compensation of 10.7Gb/s Fiber Channels. 2009 OFC/NFOEC, March 2009.
PMCC_DIV60G 60GHz Prescaler. Pacific MicroCHIP Corp. Evaluation Report – White Paper. 2008
A 0.36W 6b up to 20GSps DAC for UWB Wave Formation in IEEE ISSCC Dig. Tech. Papers, pp. 24–26. Feb. 2006