• Cadence: RTL Compiler, SOC Encounter, SimVision, QRC
  • Cadence: RTL Compiler, SOC Encounter, SimVision, QRC
  • Synopsys: Design Compiler, Prime Time, Tetra Max
  • Mentor Graphics: Calibre, Model Sim


  • CMOS: 7nm, 16nm, 22nm SOI, 28nm, 40nm, 45nm SOI, 65nm, 130nm, 180nm, 350nm from TSMC, GF, Samsung, TowerJazz, XFAB.
  • SiGe: 0.13um, 0.18um, 0.35um from GF, TowerJazz.

Digital Design

  • Full backend cycle from RTL to GDS
  • Full-custom/Semi-custom RTL design
  • Test bench preparation
  • Hardware description languages: VHDL, Verilog
  • Layout floorplanning, partitioning
  • Place-route and optimization
  • Clock tree synthesis optimization
  • Detail timing analysis
  • Location aware on-chip variation analysis
  • Layout area minimization
  • Crosstalk/noise analysis and mitigation
  • Parasitic extraction, back annotation
  • Digital content integration within analog flow and vice versa
  • Support in design/verification tools setup
  • LVS/DRC rule deck customization
  • Custom components and Cells design
  • TCL, PERL and other script languages based design automation
  • Reliable/efficient off-site design space integration with customer’s design space
  • Tapeout procedures


  • RTL Coding
  • Functional Verification / Simulation
  • Logical Synthesis
  • Physical implementation
  • Design Planning
  • Clock-tree synthesis
  • Placement and routing
  • RC Extraction
  • Design rules checking
  • Static timing analysis
  • Functional Verification after RC extraction
  • Insertion of test structures and test pattern generation
  • Sign off Formal Verification
  • Sign off check: LVS, DRC, RC extraction

Design Porting

  • Migration to other processes/nodes
  • Migration to other design platforms
  • Full migration: re-synthesis and layouts
  • Semi-automated migration
  • Post-migration parameters optimization, functionality expansion, power reduction