PACIFIC MICROCHIP is a privately held IC design company founded in 2006 and headquartered in Los Angeles, California, USA. Since 2006 we have designed a number of ASICs for fiber-optic and wireless communications, precision instrumentation and imaging.

We Use The Following Processes

CMOS 0.35u, 0.18u, 0.13u, 65nm, 45nm, 40nm, 28nm from TSMC, GF, GFUS and TowerJazz Semiconductor
SiGe 0.35u, 0.18u, 0.13u from GFUS and TowerJazz Semiconductor.

Our Company's Expertise Includes:

DESIGN complete Digital/Analog/RF/Mixed signal ASICs from spec to silicon.
ASSIST at any step of IC design, integration, characterization.
INTEGRATE Analog and digital blocks provided by customer or third party.
DELIVER IP blocks ready for integration.
PROVIDE on-site or off-site assistance and support.

For more information, please visit our SERVICES page.

Analog, RF & Signal

A/D, D/A Converters
Integer/Fractional N Frequency Synthesizers
Phase Locked Loops (PLLs)
OpAmps
Band-gap References
Regulators
Low Noise Amplifiers
Variable Gain Amplifiers
Image Sensors Readout ICs (ROICs)
Jitter Filters (Clock Cleaner)
BPSK and QPSK Modulators/De-modulators

High Speed

Frequency Dividers up to 70GHz
1:32 Deserializers up to 40Gb/s
32:1 Serializers up to 40Gb/s
Limiting Amplifiers up to 40 GHz
Clock Data Recovery up to 40Gb/s
Multifunctional Encoders 10-20 Gb/s
NRZ to RZ Encoders 10-20 Gb/s
EML Drivers 10-12 Gb/s
Variable Gain Amplifiers up to 40GHz
Continuous Time Filters up to 10 GHz
Low-noise VCOs up to 10-30 GHz

Layout Design/Optimization

Full-custom/Semi-custom layout design
Migration to other technologies/nodes
Layout design for high speeds
Calibre &aml; Assura verification
Optimization – parasitic effect minimization
ASIC integration & tapeout
Voltage drop analysis and minimisation
Thermo-electrical simulations

Digital

RTL design (front end)
Synthesis, timing closure (back end)
FPGA to ASIC migration
Serial interfaces RTL design
State machines RTL design
Scan insertion
DFT
Equivalency checking, verifications
Integration with analog content
Timing closure between analog and digital blocks.