LAYOUT DESIGN

Tools

  • Cadence: Virtuoso, PVS, Assura, QRC, Encounter
  • Mentor Graphics: Calibre

Processes

  • CMOS 0.35u, 0.18u, 0.13u, 65nm, 45nm, 40nm, 28nm from TSMC, GFUS and TowerJazz Semiconductor.
  • SiGe 0.35u, 0.18u, 0.13u from GFUS and TowerJazz Semiconductor.

Physical Design

  • Full-custom/Semi-custom layout design
  • Full cycle from schematic to GDS
  • High-speed oriented design
  • Analog/precision oriented layout design
  • Layout area minimization
  • RCL parasitics aware layout optimization
  • Symmetry/matching techniques
  • Metal mask change aware design option
  • Crosstalk/noise analysis and mitigation
  • Reliability/electromigration aware design
  • Thermal effects aware floorplanning
  • Parasitic extraction, back annotation
  • Automated power planes generation

Design Flow

  • Support in design/verification tools setup
  • LVS/DRC rule deck customization
  • Custom components and PCells design
  • Cadence SKILL based design automation
  • Reliable/efficient off-site design space integration with customer’s design space
  • Tapeout procedures
  • Digital content integration within analog flow and vice versa
  • Semi-automated metal de-stressing
  • Semi-automated current density check
  • Accurate IR drop analysis
  • Temperature gradient analysis